By Juan J. Becerra, Eby G. Friedman
Analog layout matters in electronic VLSI Circuits and Systems brings jointly in a single position vital contributions and updated study ends up in this fast-paced quarter.
Analog layout matters in electronic VLSI Circuits and Systems serves as a good reference, offering perception into the most not easy examine concerns within the field.
Read or Download Analog Design Issues in Digital VLSI Circuits and Systems: A Special Issue of Analog Integrated Circuits and Signal Processing, An International Journal Volume 14, Nos. 1/2 (1997) PDF
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Extra info for Analog Design Issues in Digital VLSI Circuits and Systems: A Special Issue of Analog Integrated Circuits and Signal Processing, An International Journal Volume 14, Nos. 1/2 (1997)
The relationships for getting logic states out of node voltages are straight forward; a simple conversion from circuit to logic-timing level is all that is required. For the coupling of the different simulation modes in BRASIL an effective interaction of the event-driven timing simulator and the circuit simulator with its time step controlling scheme is essential. While the timing algorithms remain the main simulators, the eventdriven scheme is preserved. If an event for the input of a subcircuit has been marked for the circuit simulator, an operation-point analysis has to be performed.
It is built of 8 half- and 48 full- 4 . JJ. lt) f v/V /( 0. 0n t/s Fig. 16. output node outl. SO / 307. SOn 310. OOn 312. SOn t/s Fig. 17. Results of a mixed-mode-simulation. 5 0. 0 ··-' 302. SOn 30S. OOn 5 . 00n t/s Fig. 14. Output voltage ofEXOR gate. inl o----1 in2o----t adders, with 2464 transistors and 1250 nodes. For BRASIL, 20 subcircuits together with 300 transistors are chosen to be simulated with the circuit simulator. In Figure 17 a section of the voltage curve at an output node of the multiplier is shown.
Furthermore, a rule-based investigation of the transistor functions separates logic gates, transfergates and analog blocks. The analog blocks and subcircuits with bipolar transistors are automatically labeled for the circuit simulator. A partitioning is also applied, which uses well defined borders to prevent these parts from spreading over the entire network. The timing simulator performs a dynamic partitioning during the simulation. Boundaries of a subcircuit are defined by input nodes, gate terminals of MOS transistors and drain- and source-terminals of transistors in the "OFF"-region with Vgs < V1 .
Analog Design Issues in Digital VLSI Circuits and Systems: A Special Issue of Analog Integrated Circuits and Signal Processing, An International Journal Volume 14, Nos. 1/2 (1997) by Juan J. Becerra, Eby G. Friedman